Synthworks' Advanced VHDL for Synthesis and Verification

Schedule
Core Courses
	Comprehensive VHDL Intro (4 Days)

	VHDL Testbenches & Verification (4 Days)

	VHDL Synthesis (4 Days)

Custom Courses
	VHDL Intro for Verilog (1-4 Days)

	Intermediate VHDL for Synthesis (2 Days)

	Advanced VHDL for Synthesis (2 Days)

	Intermediate VHDL (3-5 Days)

	Advanced VHDL (3-5 Days)

	Quick VHDL Intro (2 Days)

VHDL Papers

VHDL Links

Advanced VHDL for Synthesis and Verification
Advanced Level. 3-5 Days: 50% Lecture, 50% Labs

Course Overview
This is a custom class in which course materials are selected from the following core courses:

Advanced VHDL Coding for Synthesis (2 days)
VHDL Testbenches and Verification (4 days)

Course Outline A full 5 day course is as follows

	Day 1, Synthesis Module AdvSyn1 Subprograms for Synthesis Advanced Combinational Logic Advanced Sequential Logic Parameterizing Designs		Day 3, Testbench Module Tb1 Testbench Overview Basic Testbenches Transactions and Subprograms Modeling for Verification VHDL IO
	Day 2, Synthesis Module AdvSyn2 Advanced Arithmetic Architecting Hardware TxPort Statemachine Fixed and Floating Point Types		Day 4, Testbench Module Tb2 Lab Review: Testing with subprograms Transaction-Based BFM Execution and Timing Elements of a Transaction-Based BFM
			Day 5, Testbench Module Tb3 Configurations and Simulation Management Subblock to System-Level Tests Creating Tests Modeling RAM

Customization Possibilities

5 Day Class: AdvSyn1, AdvSyn2, Tb2, Tb3, Tb4
4 Day Class: AdvSyn1, AdvSyn2, Tb1, Tb2
3 Day Class: AdvSyn1, AdvSyn2, Tb1
4 Day Class: AdvSyn1, AdvSyn2, Tb3, Tb4 – only if previously took Tb2

Note it is also possible to include materials from the Intermediate VHDL Coding for Synthesis class.

Prerequisites
Students taking this course should have significant experience designing and testing digital logic with VHDL or have taken the course:

Intermediate VHDL for Synthesis and Verification - 3-5 days

Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.