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Advanced VHDL Coding for Synthesis
Advanced Level. 2 Days: 50% Lecture, 50% Labs

Course Overview
An in-depth study of advanced VHDL techniques for FPGA and ASIC design engineers.

Class topics focus on coding techniques, advanced language features (subprograms, generics, generate, packages), issue identification and problem solving. Lecture sections contain short exercises for immediate learning feedback. Labs, which account for approximately 50% of class time, give students the opportunity to experiment with different coding styles and problem solving techniques using the synthesis tool.

This class is the second half of VHDL Coding for Synthesis

Intended Audience
Recommended for experienced VHDL designers who need in-depth knowledge on synthesis coding techniques.

Course Objectives
Upon completion of this course, students will be able to:
  • Use advanced VHDL constructs to simplify the coding process
  • Understand and avoid problematic coding styles
  • Identify and solve synthesis issues using VHDL coding techniques
  • Force a synthesis tool to create the desired logic structure

Course Outline
      Day 1, Module AdvSyn1
Subprograms for Synthesis
Advanced Combinational Logic
Advanced Sequential Logic
Parameterizing Designs

      Day 2, Module AdvSyn2
Advanced Arithmetic
Architecting Hardware
TxPort Statemachine
Fixed and Floating Point Types


Prerequisites
Students taking this course should have working knowledge of digital circuits and prior exposure to VHDL through experience or the course: Other Recommended Courses
Students may also be interested in the following companion course: Customization
All of our courses can be customized to meet your specific needs. For some ideas, see customized courses.

Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.


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