Date: Thursday, October 3, 2013
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect
Verification can consume a good portion of a design cycle. What is needed is a methodology that facilitates thorough testing and timely completion. Attempting to achieve this, other verification methodologies (such as SystemVerilog’s UVM) have gone in a direction that requires OO techniques and a specialist in verification. This webinar provides an overview of a VHDL methodology that is simple, powerful, and readable by both design and verification engineers. In addition, it supports all important testbench features: TLM (transaction level modeling), constrained random, functional coverage, intelligent testbenches, OSVVM, reuse, interfaces, scoreboards, concurrency and synchronization, and memory models.
All of the VHDL techniques presented in this webinar work on a basic VHDL simulator that supports VHDL-2008.