Category Archives: Testbench

Announcing OSVVM™ 2015.03

OSVVM 2015.03 is a minor release that updates only AlertLogPkg. All other packages remain unchanged.

In AlertLogPkg, added AlertIfEqual, AlertIfNotEqual, and AlertIfDiff (file). Added ReadLogEnables to initialize LogEnables from a file. Added ReportNonZeroAlerts. Added PathTail to extract an instance name from MyEntity’PathName. Added ReportLogEnables and GetAlertLogName. See AlertLogPkg_User_Guide.pdf for details.

For hierarchy mode, AlertIfEqual, AlertIfNotEqual, and AlertIfDiff have the AlertLogID parameter first. Overloading was added for AlertIf and AlertIfNot to make these consistent. Now with multiple parameters, it is easier to remember that the AlertLogID parameter is first. The older AlertIf and AlertIfNot with the AlertLogID as the second parameter were kept for backward compatibility, but are considered bad practice to use in new code.

Added ParentID parameter to FindAlertLogID. This is necessary to correctly find an ID within an entity that is used more than once.

Bug fix: Updated GetAlertLogID to use the two parameter FindAlertLogID. Without this fix, Alerts with the same name incorrectly use the same AlertLogID.

Bug fix: Updated NewAlertLogRec (called by GetAlertLogID) so a new record gets Alert and Log enables based on its ParentID rather than the ALERTLOG_BASE_ID. Issue, if created an Comp1_AlertLogID, and disabled a level (such as WARNING), and then created a childID of Comp1_AlertLogID, WARNING would not be disabled in childID.

Bug fix: Updated ClearAlerts to correctly set stop counts (broke since it previously did not use named association). Without this fix, after calling ClearAlerts, a single FAILURE would not stop a simulation, however, a single WARNING would stop a simulation.

Since 2015.01 has known bugs, it has been deleted from the downloads page.

OSVVM™ Webinar + World Tour Dates

Webinar Thursday June 26, 2014
OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests.  This simplified approach allows you to utilize advanced randomization techniques when you need them and easily mix advanced randomization techniques with directed, algorithmic, and file-based test generation techniques.  Best of all, OSVVM is free and works in most VHDL simulators.

Europe Session 3-4 pm CEST 6-7 am PDT 9-10 am EDT Enroll with Aldec
US Session 11 am-12 Noon PDT 2-3 pm EDT 8-9 pm CEST Enroll with Aldec
 

OSVVM World Tour Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

July 14-18 Munich, Germany Enroll with eVision Systems
July 21-25 Bracknell, UK Enroll with FirstEDA
August 18-22 and September 2-5 online class Enroll with SynthWorks
August 25-29 Portland, OR (Tigard/Tualatin) Enroll with SynthWorks
September 15-19 Gothenburg, Sweden Enroll with FirstEDA
October 20-24 Bracknell, UK Enroll with FirstEDA
October 27-31 and November 10-14 online class Enroll with SynthWorks
November 17-21 Baltimore, MD (BWI Area) Enroll with SynthWorks
December 1-5 and December 17-21 online class Enroll with SynthWorks
 

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

Webinar: VHDL Testbench Techniques that Leapfrog SystemVerilog

Date: Thursday, October 3, 2013

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

Abstract:
Verification can consume a good portion of a design cycle. What is needed is a methodology that facilitates thorough testing and timely completion. Attempting to achieve this, other verification methodologies (such as SystemVerilog’s UVM) have gone in a direction that requires OO techniques and a specialist in verification. This webinar provides an overview of a VHDL methodology that is simple, powerful, and readable by both design and verification engineers. In addition, it supports all important testbench features: TLM (transaction level modeling), constrained random, functional coverage, intelligent testbenches, OSVVM, reuse, interfaces, scoreboards, concurrency and synchronization, and memory models.

All of the VHDL techniques presented in this webinar work on a basic VHDL simulator that supports VHDL-2008.

VHDL Functional Coverage is more capable than SystemVerilog

This is a continuing series of posts on OSVVM and functional coverage. If you are just getting started, you may wish to start with the OSVVM page.

When writing functional coverage it is important to be able to capture all the details of a model. With item (aka point) coverage, both VHDL and SystemVerilog do a good job. However with cross coverage, if the model requires more than a simple Cartesian product, SystemVerilog falls short. OSVVM, on the other hand, offers a rich cross coverage capability.

In SystemVerilog functional coverage is modeled as a language based declaration. To model cross coverage in SystemVerilog, one starts by declaring item (aka point) coverage for each dimension in the cross. The cross coverage is then declared in terms of the defined item coverage. If the cross coverage is more complicated than a simple Cartesian product, a set of “and” and “or” masking operations are used to filter out items from the cross product. This results in an awkward, limited, and verbose capture of the functional coverage model.

In VHDL’s OSVVM, functional coverage is implemented as a data structure.  The functional coverage model is captured incrementally using any sequential code (if, loop, …).  As long as the entire model is captured before we start collecting coverage, we can use as many calls to AddBins or AddCross as needed.

Simple Cartesian product type coverage can be captured in a concise, single line call, such as the one used in my blog post Functional Coverage Made Easy with VHDL’s OSVVM. Note that item coverage did not need to be declared first.

ACov.AddCross( GenBin(0,7), GenBin(0,7) );

When the coverage modeling is more complicated, we can solve it piecewise using multiple calls to Addbins or AddCross to define the model. The following item coverage example uses three calls to create item coverage.

Bin1.AddBins(GenBin( 1, 3 )) ;
Bin1.AddBins(GenBin( 4, 252, 2 )) ;
Bin1.AddBins(GenBin(253, 255 )) ;

The output of GenBin is a single dimensional array value. As a result, concatenation can be used to join bins. Hence we can rewrite the above bins in a single line as shown below. Note I only recommend doing something like this when it increases readability.

Bin1.AddBins( GenBin(1, 3) & GenBin(4, 252, 2) & GenBin(253, 255)) ;

Since functional coverage is modeled using sequential code, writing conditional coverage or using iteration is simply a matter of writing the code. The following uses a boolean generic, gFAST_TEST, to determine whether to cover the entire input space or just a subset of it for a fast test.

if gFAST_TEST then
  ACov.AddCross( GenBin(0,3), GenBin(0,3) ); -- 4x4 Fast Model
else
  ACov.AddCross( GenBin(0,7), GenBin(0,7) ); -- 8x8 Complete Model
end if ;

In our VHDL Testbenches and Verification class you will get hands on experience writing functional coverage and using it to shape stimulus generation.

OSVVM, VHDL’s Leading-Edge Verification Methodology

At its lowest level, Open Source VHDL Verification Methodology (OSVVM) is a set of VHDL packages that simplify implementation of functional coverage and randomization.  OSVVM uses these packages to create an Intelligent Coverage verification methodology that is a step ahead of other verification methodologies, such as SystemVerilog’s UVM.

Continues on the OSVVM static page:  http://www.synthworks.com/blog/osvvm/