VHDL Testbenches

This blog explores VHDL testbench techniques that provide a competitive, if not superior, approach to other verification languages such as SystemVerilog or ‘e’.

Verification can consume a good portion of a design cycle.   What we need is a methodology that facilitates thorough testing and timely completion.   Attempting to achieve this, other verification methodologies, such as SystemVerilog’s UVM, have gone in a direction that requires OO techniques and a specialist in verification.

The VHDL methodology explored here achieves thorough testing and timely completion while at the same time is simple and readable by both design and verification engineers.  At the heart of this methodology is transaction level models (TLM).   Using TLM simplifies the mixing of directed, algorithmic, file based, constrained random, and intelligent coverage based testing.

As a programming language VHDL has all of the capability it needs to create powerful utilities essential in a verification environment.  Constrained random, functional coverage, and intelligent testbench (Intelligent Coverage™) capabilities are discussed in detail in our OSVVM blog.  Our utilities for interfaces, scoreboards, synchronization, and memory models is covered in detail in VHDL Testbenches and Verification class.

I will expand on testbench topic is blog posts.  The following is list contains links to posts and identifies future topics.

  • Testbench Architecture
  • Transactions
  • Writing Tests
  • Randomization
  • Functional Coverage
  • Intelligent Coverage is More Capable
  • Coverage Closure is Faster with Intelligent Coverage
  • Self-Checking & Scoreboards
  • Dispelling FUD