ASIC and FPGA Design and Verification Contract Status
Current Assignment and Availability
I am currently available for consulting and contracting work. Work can be done from my office in Tigard (Portland), Oregon or on-site at your location. I give preference to challenging projects. How can I help?
Contact me for up to date information.
I have designed and verified ASICs and FPGAs from system concepts to board test. As a result, I am comfortable with most ASIC and FPGA tasks.
- Hardware System Architecture
- ASIC / FPGA Detailed Architecture
- ASIC and FPGA RTL Coding
- VHDL code review
- System verification planning
- System-level, Transaction-based testbench implementation
- Transaction-based testbench model development
- Methodology & Tool Flow Planning
- Design infrastructure planning and implementation
- Custom program and script development to automate the design process
- VHDL methodology review
Tool and Vendor Experience
- Problem Solving (code, tools, methodology)
- VHDL Training
- Model Technology, MTI Simulator
- Synplicity Synplify Synthesis Tool
- Mentor/Exemplar Synthesis Tools
- Synopsys Design Compiler, FPGA Compiler, and VSS Simulator
- Mentor Graphics Leonardo Synthesis Tool
- SCCS, RCS revision control tools
- ASIC Vendors: Fujitsu, OKI, TI, ST, Honeywell
- FPGA Vendors: Altera, Xilinx, Actel
As part of my past assignments I have done the following:
- Defined the Hardware System Architecture
- Written Hardware Architecture Specifications.
- Written Hardware Implementation Specifications.
- Written Hardware - Software Interface Specifications.
- Intel 80486 CPU interface.
- SDRAM Controller.
- DPRAM Controller.
- EDO DRAM Controller.
- IEEE 1284 Parallel Port (Host).
- HP MIO Interface (HP Printer internal port).
- FIFOs, both memory and register based.
- T1/E1 plus ATM processing logic for IMA ATM board using two Altera FPGAs
- Written a IEEE 1284 parallel port peripheral behavioral model.
- Model included additional states for error insertion /generation.
For more details see my resume.
- Transaction-based system-level verification of ASICs and FPGAs
- Synopsys (LMG) Smart Models
- Internally developed models
VHDL or Verilog
To date, all of my HDL based ASIC design has been with VHDL. Some day if the opportunity presents itself I would like to try my hand at Verilog. For my first VHDL design, I learned VHDL, Synopsys, and developed an Actel FPGA in 6 months. I am confident that learning Verilog will come as easily as VHDL.
The SynthWorks offices are in Tigard (Portland), Oregon.
Work can be done from my office or on-site at your location.
Preference is given to work done in Portland area (my site or yours).
Contact me for details.
I also give preference to non-US locations. As part of my consulting activities with Zycad, I worked in France and would like to go back. Caution, my French is still only good enough to get dinner and a laugh.
Yoga, Ultimate Frisbee, Kayaking, Skiing
To view Mr. Lewis' biography, click here.
To view Mr. Lewis' resume, click here.