Schedule Core Courses Comprehensive VHDL Intro (4 Days) VHDL Testbenches & Verification (4 Days) VHDL Synthesis (4 Days) Custom Courses VHDL Intro for Verilog (1-4 Days) Intermediate VHDL for Synthesis (2 Days) Advanced VHDL for Synthesis (2 Days) Intermediate VHDL (3-5 Days) Advanced VHDL (3-5 Days) Quick VHDL Intro (2 Days) VHDL Papers VHDL Links SynthWorks' VHDL Papers Published Papers Conference Paper Title Date MARLUG 2006 "Accellera VHDL 2006 Standard 3.0" Updates to VHDL done as part of the Accellera VHDL 2006 Standard 3.0.   Standard is done and ready for industry adoption. General Overview:                        Slides Color       Slides B&W Fixed and Floating Point Types:    Slides Color       Slides B&W October, 2006 MAPLD 2005 "Fixed and Floating Point Packages" A mini-tutorial on VHDL Fixed and Floating Point Math Packages. Slides Color       Slides B&W September, 2005 Several "VHDL-200X: The Future of VHDL" Papers describing work prior to the completion of Accellera VHDL 2006 Standard 3.0 Next VHDL Revision:    DesignCon East Sept 2005:     Slides    MAPLD Sept 2005:     Slides    Mentor User2User Apr 2005:     Slides   Paper    DVCon Feb 2005:     Slides   Paper    MARLUG Oct 2004,   FT Update:     Slides VHDL 200X Working Group Organization:    DesignCon Feb 2004:     Slides   Paper    MAPLD Sept 2003:     Slides   DVCon 2004 "IEEE 1076.6-2004: VHDL Synthesis Coding Styles for the Future" 1076.6 seeks to gain portability of VHDL RTL coding styles by standardizing coding styles that compliant EDA vendors are required to implement. It also specifies coding styles that compliant IP/model developers must use to achieve portability. This paper presents effective coding styles that have resulted from the 1076.6-2004 effort. This effort brings you multiple edge register coding styles (to match today's FPGAs), more effective/ efficient register coding styles (concurrent code, subprograms, and expanded usage of wait), ROM and RAM coding styles, and additional attributes to control the intent of coding styles. Slides     Paper March 2-3, 2004 MAPLD 2003 "VHDL Math Tricks of the Trade" A mini-tutorial on VHDL types (esp. unsigned and signed), packages, strong typing rules, conversions, ambiguous expressions, and math tricks. Slides September 9-11, 2003 DVCon 2003 "Enhancements to VHDL's Packages" Gives updates on upcomming changes to packages Numeric_Std (IEEE 1076.3) and Std_Logic_1164 (IEEE 1164). Paper     Slides February 25, 2003 DesignCon 2003 "Accelerating Verification Through Pre-Use of System-Level Testbench Components" Presents a methodology for "pre-using" system-level testbench components and shows an implementation of the corresponding system-level, transaction-based testbench. Paper     Slides January 28, 2003 MAPLD 2002 "Coding a 40 x 40 Multipler" Explores coding styles for coding a pipelined multiplier. Paper     Slides-Color     Slides-B&W September 2002 HDLCON 2002 "Extensions to the VHDL RTL Synthesis Standard" VHDL RTL Coding styles were first standardized in 1999.  This paper gives insight into the future direction of the standard.  Co-authored paper with Vinaya Singh of Cadence. Paper March 2002 Published Tutorials (not available for download) Conference Tutorial Title Date DVCon 2004 and DesignCon 2004 "VHDL Transaction Based Verification" March 2004 February 2004 FDL 2001 "VHDL Coding Styles for Hardware Design" September 2001 HDLCON 2001 VHDL Coding Styles for Hardware Design March 2001 IHDL 1999 Hardware Verification with VHDL March 1999
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