Core Courses
Our suggested courses
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Comprehensive VHDL Introduction - 4 Days
Basic Level, 50% Lecture, 50% Labs
An in-depth introduction to VHDL and its application to design and verification of digital hardware (FPGAs and ASICs). Students will gain a strong foundation in VHDL RTL and testbench coding techniques. Lectures contain numerous examples that show both syntax and coding style guidelines. Labs give students hands-on experience writing RTL code, writing testbenches, running your simulator and synthesis tools, and programming our FPGA based lab board. Recommended as a first course for design and verification engineers who need a solid foundation in VHDL.
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VHDL Testbenches and Verification - 4 Days
Advanced Level, 50% Lecture, 50% Labs
An in-depth study of advanced VHDL coding styles and methodologies to
verify digital hardware (FPGAs and ASICs).
This course starts with simple testbenches and progressively
increases the level of abstraction.
Along the way students learn about subprogram usage, TEXTIO,
modeling issues, transaction-based tests,
data structures (linked-lists, scoreboards, memories), algorithmic and
random test generation, protocol checking, result checking, and handshaking methods.
The final result is a transaction-based, system-level, self-checking test environment.
Our test methodology shows how to pre-use the system-level
test environment for subblock tests.
Labs track with lecture giving students the opportunity to apply what they learn.
As new verification features are integrated into VHDL as part of the VHDL-2006 language revision effort, we expect this course to become 4 days in length.
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VHDL Coding for Synthesis - 4 Days
Advanced Level, 50% Lecture, 50% Labs
An in-depth study of VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic. Class topics focus on mapping digital hardware structures to vendor independent VHDL code. Detailed do's and don'ts of synthesis coding styles are discussed. Lecture and laboratory materials illustrate the optimization differences achieved by different VHDL coding styles. Students will learn proven coding practices that result in smaller and faster designs. The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.
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Custom Courses
Common combinations and customizations of our core courses.
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VHDL Introduction for Verilog Designers - 1-4 Days
Basic Level
Comprehensive VHDL Introduction customized for students with Verilog experience.
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Intermediate VHDL Coding for Synthesis - 2 Days
Intermediate Level, 50% Lecture, 50% Labs
An in-depth study of VHDL coding styles, methodologies, and design techniques used to efficiently synthesize digital hardware (ASICs and FPGAs). Class topics focus on mapping digital hardware structures to vendor independent VHDL code. Detailed do's and don'ts of synthesis coding styles are discussed. Lecture and laboratory materials illustrate the optimization differences achieved by different VHDL coding styles. Students will learn proven coding practices that result in smaller and faster designs. The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design.
This class is the first half of
VHDL Coding for Synthesis
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Advanced VHDL Coding for Synthesis - 2 Days
Advanced Level, 50% Lecture, 50% Labs
An in-depth study of advanced VHDL RTL coding techniques for FPGA and ASIC design engineers. Class topics focus on coding techniques, advanced language features (subprograms, generics, generate, packages), issue identification and problem solving. Lecture sections contain short exercises for immediate learning feedback. Labs, which account for approximately 50% of class time, give students the opportunity to experiment with different coding styles and problem solving techniques using the synthesis tool.
This class is the second half of
VHDL Coding for Synthesis
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Intermediate VHDL for Synthesis and Verification - 3-5 Days
Intermediate Level, 50% Lecture, 50% Labs
Covers both testbench and intermediate RTL coding topics. Covers all topics from Intermediate VHDL Coding for Synthesis and the VHDL Testbenches and Verification class.
In a public venue, we offer these courses on the same week and allow students to sign?up for each separately. For on-site classes, it is possible to shorten either the synthesis or verification portion of the class.
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Advanced VHDL for Synthesis and Verification - 3-5 Days
Advanced Level, 50% Lecture, 50% Labs
Covers both testbench and advanced RTL coding topics. Covers all topics from Advanced VHDL Coding for Synthesis and the VHDL Testbenches and Verification class.
In a public venue, we offer these courses on the same week and allow students to sign?up for each separately. For on-site classes, it is possible to shorten either the synthesis or verification portion of the class.
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Quick VHDL Introduction - 2 Days
Basic Level, 60% Lecture, 40% Labs
Comprehensive VHDL Introduction shortened for support engineers and managers who only need to understand the basics of using VHDL in a design environment. Only recommended for design and verification engineers when they plan on immediately following it with additional training.
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Your Customized Course
Didn't find what you are looking for? Contact us and we can customize a class for you.
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