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Day 1
A Quick Introduction
Lab 1: Simple RTL and Testbench
Data Types
Operators
Concurrent Statements
Sequential Statements
Lab 2: Clock and Reset
Lab 3: RTL and Testbench
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Day 2
Statemachine Coding Techniques
Lab4: RTL Code
Data Objects
Designing with VHDL
Lab 5: Coding an FSM
Lab 6: Creating Hierarchy
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