SynthWorks' VHDL Testbenches and Verification

Schedule
Core Courses
	Comprehensive VHDL Intro (4 Days)

	VHDL Testbenches & Verification (4 Days)

	VHDL Synthesis (4 Days)

Custom Courses
	VHDL Intro for Verilog (1-4 Days)

	Intermediate VHDL for Synthesis (2 Days)

	Advanced VHDL for Synthesis (2 Days)

	Intermediate VHDL (3-5 Days)

	Advanced VHDL (3-5 Days)

	Quick VHDL Intro (2 Days)

VHDL Papers

VHDL Links

VHDL Testbenches and Verification
Advanced Level. 4 Days: 50% Lecture, 50% Labs

Course Overview
Students will gain in-depth knowledge of advanced VHDL coding styles and methodologies to verify digital hardware (ASICs and FPGAs). Test topics range from the creation of simple testbenches through the creation of a transaction-based, system-level, self-checking test testbench. Transaction-based testbenches simplify test development and significantly reduce the time it takes to write tests.

This course starts by showing how to create a simple test environment and progressively adds to it. Along the way students learn about subprogram usage, TEXTIO, modeling issues, transaction-based tests, data structures (linked-lists, scoreboards, memories), algorithmic and random test generation, protocol checking, result checking, and handshaking methods. Once putting the basics in place, the course starts looking at the system-level testbenches. A system-level testbench replicates the environment of the design under test. Each interface in the system is implemented by a behavioral model. Lecture and laboratory examples progressively add timing checking, protocol checking, data input (source), data result checking, and data synchronization facilities to the models.

Intended Audience
VHDL Testbenches and Verification is recommended for experienced VHDL designers who need in-depth knowledge on verification coding techniques.

Course Objectives
Upon completion of this course, students will be able to:

Create a transaction-based, system-level, self-checking test environment
Use textio to read files and write useful messages
Write bus functional models for testbenches
Use subprograms to abstract interface actions (CpuRead, CpuWrite)
Understand how VHDL executes a model
Plan the test process from subblock to systel-level tests
Know how to create a test plan
Use VHDL configurations to simplify and increase the effectiveness of tests
Model RAM

Course Outline

	Day 1, Module Tb1 Testbench Overview Basic Testbenches Transactions and Subprograms Modeling for Verification VHDL IO		Day 3, Module Tb3 Lab Review: UartTx BFM Creating Tests Data Structures for Verification Constrained Random Tests
	Day 2, Module Tb2 Lab Review: Testing w/ subprograms Transaction-Based BFM Execution and Timing Elements of a Transaction-Based BFM		Day 4, Module Tb4 Test Plans Configurations and Simulation Management Modeling RAM Transaction-Based BFM, Part 2

Prerequisites
Students taking this course should have prior exposure to VHDL through experience or the course:

Comprehensive VHDL Introduction - 4 days

Other Recommended Courses
Students may also be interested in either or both of the following companion courses:

VHDL Coding for Synthesis - 4 days

Customization
All of SynthWorks' courses can be customized to meet your specific needs.

Training Approach
This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code.