Director of Training - SynthWorks Design, Inc.
Jim Lewis, the founder of SynthWorks, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting.
Mr. Lewis is the architect and principal developer of Open Source VHDL Verification Methodology (OSVVM), the #1 VHDL Verification Methodology.
The OSVVM utility library provides similar capabilities to other verification languages, such as SystemVerilog + UVM.
OSVVM capabilities include transaction level modeling, error handling and conditional messaging (debug messages+), functional coverage, constrained random and Intelligent Coverage Random test generation, data structures (scoreboards, ...), and basic utilities (synchronization, clock generation, ...).
The OSVVM model library provides common models such as Axi4Lite, AxiStream, and UART.
The intention of OSVVM goes beyond being simple and powerful —
OSVVM makes verification environments easy, readable, and fun.
Mr. Lewis was previously employed with Zycadís Protocol division where he worked as an on-site VHDL trainer, methodology consultant, and ASIC designer. As a representative from Zycad, he provided VHDL training, methodology consulting, and ASIC design for Lockheed Sanders in their development of 22 ASICs for the F22 program. On another assignment for Zycad, he worked as a VHDL trainer, Synopsys synthesis trainer, problem solver, and ASIC designer for SGS Thomson in their development of a Video Codec chip. In addition to other responsibilities, Mr. Lewis acted as an on-site focal point for resolving VHDL synthesis issues for both companies.
Mr. Lewis was also employed by TRW where he designed ASICs, FPGAs, and worked as a member of their VHDL Methodology Development Group.
Mr. Lewis, who holds a BSEE, BSCEE, and MSEE from Purdue University, is a member of the IEEE and the Eta Kappa Nu, and Tau Beta Pi Honor Societies. Mr. Lewis is chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE and Accellera's VHDL standardization efforts.
To view Mr. Lewis' resume, click here.
For information about Mr. Lewis' consulting services, click here.