To understand the currents of a river,
  he who wishes to know the truth
    must enter the water.

In this blog, I share updates on  projects we support, such as Open Source VHDL Verification methodology (OSVVM) and IEEE 1076 VHDL Working Group. I also work on dispelling industry misconceptions based on old truths – such as VHDL is verbose – this was one of the things addressed in the VHDL-2008 update.

About SynthWorks

At SynthWorks, VHDL is not just the focus of our work, it is our passion. We are world leaders in VHDL verification and VHDL standards.  We offer instructor led, VHDL training classes, either on-site, at a public venue, or online.  We also provide VHDL verification consulting.

About Jim Lewis

I am SynthWorks’ principal VHDL trainer. I have twenty-eight years of design, teaching, and problem solving experience.  I am also chair of IEEE 1076 VHDL Working Group (VASG) and the principal developer of the Open Source VHDL Verification Methodology (OSVVM).