OSVVM, VHDL’s Leading-Edge Verification Methodology

At its lowest level, Open Source VHDL Verification Methodology (OSVVM) is a set of VHDL packages that simplify implementation of functional coverage and randomization.  OSVVM uses these packages to create an Intelligent Coverage verification methodology that is a step ahead of other verification methodologies, such as SystemVerilog’s UVM.

Continues on the OSVVM static page:  http://www.synthworks.com/blog/osvvm/