Announcing OSVVM™ 2015.03

OSVVM 2015.03 is a minor release that updates only AlertLogPkg. All other packages remain unchanged.

In AlertLogPkg, added AlertIfEqual, AlertIfNotEqual, and AlertIfDiff (file). Added ReadLogEnables to initialize LogEnables from a file. Added ReportNonZeroAlerts. Added PathTail to extract an instance name from MyEntity’PathName. Added ReportLogEnables and GetAlertLogName. See AlertLogPkg_User_Guide.pdf for details.

For hierarchy mode, AlertIfEqual, AlertIfNotEqual, and AlertIfDiff have the AlertLogID parameter first. Overloading was added for AlertIf and AlertIfNot to make these consistent. Now with multiple parameters, it is easier to remember that the AlertLogID parameter is first. The older AlertIf and AlertIfNot with the AlertLogID as the second parameter were kept for backward compatibility, but are considered bad practice to use in new code.

Added ParentID parameter to FindAlertLogID. This is necessary to correctly find an ID within an entity that is used more than once.

Bug fix: Updated GetAlertLogID to use the two parameter FindAlertLogID. Without this fix, Alerts with the same name incorrectly use the same AlertLogID.

Bug fix: Updated NewAlertLogRec (called by GetAlertLogID) so a new record gets Alert and Log enables based on its ParentID rather than the ALERTLOG_BASE_ID. Issue, if created an Comp1_AlertLogID, and disabled a level (such as WARNING), and then created a childID of Comp1_AlertLogID, WARNING would not be disabled in childID.

Bug fix: Updated ClearAlerts to correctly set stop counts (broke since it previously did not use named association). Without this fix, after calling ClearAlerts, a single FAILURE would not stop a simulation, however, a single WARNING would stop a simulation.

Since 2015.01 has known bugs, it has been deleted from the downloads page.

Announcing OSVVM™ 2015.01

OSVVM 2015.01 is a major release that introduces AlertLogPkg. AlertLogPkg adds Alert and verbosity control procedures that are a powerful replacement for assert statements. All OSVVM packages have replaced asserts with alerts.

VHDL assert statements have a limited form of an alert and verbosity control. Through a simulator, you can set an assertion level that will stop a simulation. Through a simulator, you can turn off some assertions from printing. However, none of this capability can be configured in VHDL, and in addition, at the end of a test, there is no way to retrieve a count of the various assertions that have occurred.

The AlertLogPkg provides Alert and Log procedures that replace VHDL assert statements and gives VHDL direct access to enabling and disabling of features, retrieving alert counts, and set stop counts (limits). All of these features can be used in either a simple global mode or a hierarchy of alerts.

Similar to VHDL assert statements, Alerts have values FAILURE, ERROR, and WARNING. Each is counted and tracked in an internal data structure. Within the data structure, each of these can be enabled or disabled. A test can be stopped if an alert value has been signaled too many times. Stop values for each counter can be set. The default for FAILURE is 0 and ERROR and WARNING are integer’right. If all test errors are reported as an alert, at the end of the test, a report can be generated which provides pass/fail and a count of the different alert values.

What differentiates AlertLogPkg from other alert and verbosity filtering packages is hierarchical alerts. Hierarchical alerts allow alerts for each model and/or each source of alerts to be accumulated and reported separately. While the whole testbench will benefit from all models using alerts, a single model can effectively use either global or hierarchical alerts.

Logs provide a mechanism for verbosity control on printing. Through simulator settings, assert has this capability to a limited degree. Verbosity control allows messages (such as debug, DO254 final test reports, or info) that are too detailed for normal testing to be printed when specifically enabled.

OSVVM 2015.01 also introduces TranscriptPkg. TranscriptPkg provides a mechanism to share a transcript file across the entire testbench. TranscriptPkg provides a shared file, TranscriptFile, and procedures TranscriptOpen, TranscriptClose, print, and writeline. Print and WriteLine print to TranscriptFile when the transcript file is open, otherwise, print to std.textio.OUTPUT. AlertLogPkg uses TranscriptPkg for all of its printing. CoveragePkg uses TranscriptPkg for all of its printing that previously went to std.textio.OUTPUT.

OSVVM 2015.01 also introduces OsvvmGlobalPkg. OsvvmGlobalPkg provides a means to set global parameters for coverage models and the AlertLogPkg.

All of the OSVVM packages have detailed user guides in the doc directory of the release. OSVVM 2015.01 is available at either SynthWorks’ or OSVVM’s download page.

There are also other Alert and verbosity control packages available. By editing the package body of AlertLogPkg, OSVVM can be configured to use the other package. By interfacing to the separate packages via the package body, only the package body needs to be recompiled and not the entire OSVVM library.

OSVVM™ 2014.07 Finally

Release 2014.07 has been posted on the downloads pages. Its main target is interfacing with requirements tools.

Added names to bins (via AddBins and AddCross). It is intended that the name match a requirement name. When using WriteBin or WriteCovHoles, if a bin name is set, it will print. For details, see Setting Bin Names in the Reporting Coverage section of the CoveragePkg Users Guide.

Enhanced WriteBin to print “PASSED” if the count is greater than or equal to the goal (AtLeast value), otherwise, it prints “FAILED”. Added a number of parameters to WriteBin to control what fields of a WriteBin report get printed. See Enabling and Disabling WriteBin fields in the Reporting Coverage section of the CoveragePkg Users Guide.

Also GenBin now takes an integer_vector parameter and returns each object in a single bin. Hence, the following will generate bins (1 to 1), (3 to 3), and (5 to 5):
Cov.AddBins( GenBin( (1, 3, 5) ) ) ;

DVCon-Europe and OSVVM

I want to apologize to anyone who was thinking I would be at DVCon-Europe this year. I was planning on attending until a colleague pointed out that my “poster presentation” was not a presentation, but instead a poster session that was only 1 hour long during lunch.

Rather than give up, I pointed out to the program committee that 60% of the FPGA market uses VHDL for verification and asked if they could find a presentation spot for my paper. My heart breaks when they claim they had no room for a VHDL presentation, but they had room for a program committee member to present both a tutorial and a paper with the title “Requirements-driven Verification Methodology.” Ironically, I would have liked to see that tutorial – I just do not think the conference benefited from both a long and short presentation on the topic.

Although VHDL is prevalent in Europe, it is sad to see DVCon-Europe omitted VHDL from both the call for papers (they solicited for SystemVerilog, SystemC, and C++) and the oral presentations.

In the end, while I wanted to attend DVCon-Europe, the travel and conference costs did not justify the minimal time that posters are actually displayed. In addition, being the only VHDL paper at the conference, convinced me that very few from the VHDL community would attend.

If you attended DVCon-Europe and are interested in learning more about my paper, OSVVM: Advanced Verification for VHDL, drop me an email (jim at, and I will arrange an on-line presentation for you and any of your colleagues who may be interested. This will be different from our normal webinars in that you will be able to ask questions via a USB headset or phone.

OSVVM™ Webinar + World Tour Dates

Webinar Thursday June 26, 2014
OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests.  This simplified approach allows you to utilize advanced randomization techniques when you need them and easily mix advanced randomization techniques with directed, algorithmic, and file-based test generation techniques.  Best of all, OSVVM is free and works in most VHDL simulators.

Europe Session 3-4 pm CEST 6-7 am PDT 9-10 am EDT Enroll with Aldec
US Session 11 am-12 Noon PDT 2-3 pm EDT 8-9 pm CEST Enroll with Aldec

OSVVM World Tour Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

July 14-18 Munich, Germany Enroll with eVision Systems
July 21-25 Bracknell, UK Enroll with FirstEDA
August 18-22 and September 2-5 online class Enroll with SynthWorks
August 25-29 Portland, OR (Tigard/Tualatin) Enroll with SynthWorks
September 15-19 Gothenburg, Sweden Enroll with FirstEDA
October 20-24 Bracknell, UK Enroll with FirstEDA
October 27-31 and November 10-14 online class Enroll with SynthWorks
November 17-21 Baltimore, MD (BWI Area) Enroll with SynthWorks
December 1-5 and December 17-21 online class Enroll with SynthWorks

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

Announcing OSVVM Release 2014.01

OSVVM release 2014.01 is now available at either SynthWorks Downloads or OSVVM Downloads.

Message handling is now handled by separate package, MessagePkg. MessagePkg must be compiled before CoveragePkg. Suggested compile order:

  • MessagePkg.vhd
  • SortListPkg_int.vhd
  • RandomBasePkg.vhd
  • RandomPkg.vhd
  • CoveragePkg.vhd

What’s new in CoveragePkg?

  • Merging of coverage databases.
  • Tracking last randomization.
  • Improved handling of overlapping count bins
  • Improved reporting on Aldec tools

What’s new in RandomPkg?

  • Added RandTime and RandReal (for sets of real numbers)
  • Added randomization of vectors: RandIntV, RandRealV, RandTimeV
  • Made sort, revsort from SortListPkg_int visible via aliases

Webinar: VHDL Testbench Techniques that Leapfrog SystemVerilog

Date: Thursday, October 3, 2013

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

Verification can consume a good portion of a design cycle. What is needed is a methodology that facilitates thorough testing and timely completion. Attempting to achieve this, other verification methodologies (such as SystemVerilog’s UVM) have gone in a direction that requires OO techniques and a specialist in verification. This webinar provides an overview of a VHDL methodology that is simple, powerful, and readable by both design and verification engineers. In addition, it supports all important testbench features: TLM (transaction level modeling), constrained random, functional coverage, intelligent testbenches, OSVVM, reuse, interfaces, scoreboards, concurrency and synchronization, and memory models.

All of the VHDL techniques presented in this webinar work on a basic VHDL simulator that supports VHDL-2008.

Functional Coverage Goals and Randomization Weights

This is a continuing series of posts on OSVVM and functional coverage. If you are just getting started, you may wish to start with the OSVVM page.

In a constrained random approach, different items can be selected more frequently by using randomization weights. Items with a higher randomization weight are selected more frequently.

In Intelligent Coverage, the same effect can be achieved by using coverage goals. A coverage goal specifies how many times a value must land in a bin before the bin is considered covered. Each bin within the coverage model can have a different coverage goal. By default, coverage goals are also used as a randomization weight. Bins with a higher goal/weight will be generated more frequently. When a bin reaches its goal, it is no longer selected by Intelligent Coverage randomization.

Coverage goals and randomization weights are an important part of the Intelligent Coverage methodology. They allow us to randomize sequences with a particular distribution. For example, if a test does packet generation, then the following code generates normal operation 70% of the time, error case 1 20% of the time, and error case 2 10% of the time.

Bin1.AddBins( 70, GenBin(0) ) ;  -- Normal Handling, 70%
Bin1.AddBins( 20, GenBin(1) ) ;  -- Error Case 1,    20%
Bin1.AddBins( 10, GenBin(2) ) ;  -- Error Case 2,    10%

StimGen : while not Bin1.IsCovered loop
  iSequence := Bin1.RandCovPoint ; 
  case iSequence is   

    when 0 =>  -- Normal Handling   -- 70%
       DoTransaction(Rec, …, NO_ERROR) ; 
       . . . 

    when 1 =>  -- Error Case 1      -- 20%
       DoTransaction(Rec, …, ERROR_CASE1) ; 
       . . . 

    when 2 =>  -- Error Case 2      -- 10%
       DoTransaction(Rec, …, ERROR_CASE2) ; 
       . . .

Each of these sequences will be selected with a weighted uniform distribution until it reaches its coverage goal.

SystemVerilog supports specifying coverage goals on the entire coverage model, but not on individual coverage bins. Since they do not use functional coverage when randomizing, they do not have a compelling need for individual coverage goals. However, this also makes them lacking in advanced features.

This post provided some basic information about coverage goals. Intelligent Coverage contains numerous advanced features that go well beyond the basic capability. For example, coverage goals can be scaled to make tests run longer using a feature called coverage targets. Convergence to a coverage goal can be smoothed out using either thresholding or different randomization weight modes.

Learn more about the advanced Intelligent Coverage features in our VHDL Testbenches and Verification class.

Webinar Recording: VHDL Intelligent Coverage using OSVVM

Did you miss our recent webinar on Intelligent Coverage and Open Source VHDL Verification Methodology (OSVVM)?

The slides and recorded webinar (on Aldec’s site) are now available. You may also be interested in reading our OSVVM Blog posts.

Looking to learn more about OSVVM and further advance your VHDL testbench skills, attend SynthWorks’ VHDL Testbenches and Verification class. In this class, we provide a super set of the OSVVM packages that facilitate transaction level modeling (tlm), self-checking, scoreboards, memory modeling, synchronization methods, functional coverage, and randomization. Our modeling approach is accessible by both verification and RTL designers.

Webinar: VHDL Intelligent Coverage using Open Source VHDL Verification Methodology (OSVVM),   July 18

Date: Thursday, July 18, 2013

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

At the lowest level, Open Source VHDL Verification Methodology (OSVVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OSVVM uses these packages to create an intelligent testbench methodology that allows mixing of “Intelligent Coverage™” with directed, algorithmic, file based, or constrained random test approaches. Having an intelligent testbench approach built into the coverage modeling puts OSVVM a step ahead of other verification methodologies, such as SystemVerilog and UVM.

Attend this webinar and learn how to utilize OSVVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.


  • What and Why OSVVM, Functional Coverage, and Randomization
  • Writing Item (Point Coverage)
  • Writing Cross Coverage
  • Constrained Random is 5X or More Slower
  • Intelligent Coverage
  • OSVVM is More Capable
  • Additional Randomization in OSVVM
  • Weighted Intelligent Coverage
  • Coverage Closure
  • OSVVM Loves any Testbench
  • Additional Methods for Verification

Benefits of OSVVM include:

  • Faster Test Construction, focus is on functional coverage
  • Faster simulations: O(Log N) faster than constrained random and no solver.
  • Goes beyond other verification languages (SystemVerilog and ‘e’)
  • Works with your current VHDL testbench
  • Uses entity and architectures for structure (just like RTL).
  • Is language accessible. Able to refine with code.
  • Readable by ALL (Verification and RTL engineers).

OSVVM is open-source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations), so you can use it today.