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DVCon-Europe and OSVVM

I want to apologize to anyone who was thinking I would be at DVCon-Europe this year. I was planning on attending until a colleague pointed out that my “poster presentation” was not a presentation, but instead a poster session that was only 1 hour long during lunch.

Rather than give up, I pointed out to the program committee that 60% of the FPGA market uses VHDL for verification and asked if they could find a presentation spot for my paper. My heart breaks when they claim they had no room for a VHDL presentation, but they had room for a program committee member to present both a tutorial and a paper with the title “Requirements-driven Verification Methodology.” Ironically, I would have liked to see that tutorial – I just do not think the conference benefited from both a long and short presentation on the topic.

Although VHDL is prevalent in Europe, it is sad to see DVCon-Europe omitted VHDL from both the call for papers (they solicited for SystemVerilog, SystemC, and C++) and the oral presentations.

In the end, while I wanted to attend DVCon-Europe, the travel and conference costs did not justify the minimal time that posters are actually displayed. In addition, being the only VHDL paper at the conference, convinced me that very few from the VHDL community would attend.

If you attended DVCon-Europe and are interested in learning more about my paper, OSVVM: Advanced Verification for VHDL, drop me an email (jim at, and I will arrange an on-line presentation for you and any of your colleagues who may be interested. This will be different from our normal webinars in that you will be able to ask questions via a USB headset or phone.